- 您现在的位置：买卖IC网 > Sheet目录892 > ZY8160G (Power-One)PROGBL CONVERT DC-DC 60A OUT THU
ZY8160 60A DC-DC Intelligent POL
8V to 14V Input ? 0.5V to 2.75V Output
Data Sheet
8.4
PWM Parameters
R/W-0
R/W-0
R/W-0
R/W-0 1)
R/W-0 1)
R/W-0 1)
R/W-0 1)
R/W-0 1)
Z-Series POLs utilize the digital PWM controller.
FRQ2
FRQ1
FRQ0
INT4
INT3
INT2
INT1
INT0
The controller enables users to program most of the
PWM performance parameters, such as switching
frequency, interleave, duty cycle, and feedback loop
compensation.
Bit 7
Bit 7:5 FRQ[2:0] : PWM Frequency Selection
000: 500kHz
001: 750kHz
010: 1000kHz
Bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
8.4.1 Switching Frequency
The switching frequency can be programmed in the
Initial value depends on the state of the Interleave Mode ( IM ) Input:
GUI PWM Controller window shown in Figure 37 or
directly via the I 2 C bus by writing into the INT register
shown in Figure 38. Note that the content of the
register can be changed only when the POL is
turned off.
Bit 4:0 INT[4:0] : Interleave position
00h: Ton starts with 0.0° Phase lag to SD Line
01h: Ton starts with 11.25° Phase lag to SD Line
02h: Ton starts with 22.50° Phase lag to SD Line
…
1Fh: Ton starts with 348.75° Phase lag to SD Line
1)
IM=Open: At POR reset the 5 corresponding ADDRESS bits are loaded
Switching actions of all POLs connected to the SD
IM=Low:
At POR reset a 0 is loaded
line are synchronized to the master clock generated
by the DPM. Each POL is equipped with a PLL and
a frequency divider so they can operate at multiples
(including fractional) of the master clock frequency
as programmed by a user. The POL converters can
operate at 500kHz, 750kHz, and 1MHz. Although
synchronized, switching frequencies of different
POLs are independent of each other. It is
permissible to mix POLs operating at different
frequencies in one system. It allows optimizing
efficiency and transient response of each POL in the
system individually.
Figure 38. Interleave Configuration Register INT
8.4.2 Interleave
Interleave is defined as a phase delay between the
synchronizing slope of the master clock on the SD
pin and PWM signal of a POL. The interleave can
be programmed in the GUI PWM Controller window
or directly via the I 2 C bus by writing into the INT
register.
Every POL generates switching noise. If no
interleave is programmed, all POLs in the system
switch simultaneously and noise reflected to the
input source from all POLs is added together as
shown in Figure 39.
Figure 39. Input Voltage Noise, No Interleave
Figure 37. PWM Controller Window
ZD-01674 Rev. 1.2, 02-Jul-10
www.power-one.com
Page 23 of 30
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
0006660012
CABLE 28AWG 148MM RED
0006660013
CABLE 28AWG 300MM RED
002679-000
CABLE 22AWG TWISTED
0082226102
RIB CBL .100 100RL TIN 2POS
0082226104
RIB CBL .100 100RL TIN 4POS
0082226115
RIB CBL .100 100RL TIN 15POS
0192520124
TIE 4 INCH 18LB NATURAL
0192520125
TIE 6.1 INCH 18LB NATURAL
相关代理商/技术参数
ZY8160G-Q1
制造商:Power-One 功能描述:
ZY8160G-R1
功能描述:DC/DC转换器 8-14Vin 60A(max) 0.5-2.75Vout 29mA RoHS:否 制造商:Murata 产品: 输出功率: 输入电压范围:3.6 V to 5.5 V 输入电压（标称）: 输出端数量:1 输出电压（通道 1）:3.3 V 输出电流（通道 1）:600 mA 输出电压（通道 2）: 输出电流（通道 2）: 安装风格:SMD/SMT 封装 / 箱体尺寸:
ZY82
制造商:FAGOR 功能描述:FAGOR S9G7A 制造商:General Instruments 功能描述:Zener Diode, Two Terminal, 82 Volt, 6.7%, DO-15
ZY82B
制造商:DIOTEC 制造商全称:Diotec Semiconductor 功能描述:Silicon Power Z-Diodes (non-planar technology)
ZY82GP
制造商:未知厂家 制造商全称:未知厂家 功能描述:2 W Glass Passivated Zener Diode
ZY8V2GP
制造商:未知厂家 制造商全称:未知厂家 功能描述:2 W Glass Passivated Zener Diode
ZY9.1
制造商:DIOTEC 制造商全称:Diotec Semiconductor 功能描述:Silicon-Power-Zener Diodes (non-planar technology)
ZY9.1V
制造商:CDIL 制造商全称:Continental Device India Limited 功能描述:SILICON GLASS PASSIVATED 2.0 WATT ZENER DIODES